The present invention relates generally to testing integrated circuits. More particularly, the present invention relates to scan testing of integrated circuits.
Modern integrated circuits generally comprise a large number of circuit elements. It is desirable to test these circuit elements in order to ensure the proper operation of the integrated circuit. However, the number of test points (that is, locations where signals can be measured) is limited by the number of terminals of the integrated circuit, which is far less than the number of circuit elements to be tested.
Consequently, designers of modern integrated circuits often employ a test technique referred to herein as “scan testing.” FIG. 1 shows a conventional integrated circuit 100 designed to permit scan testing of logic circuits 102. According to this technique, integrated circuit 100 includes a scan chain 104 comprising a number of storage elements such as scan flip-flops (SFF) 106A through 106N that can be loaded with a test vector. The test vector is a binary number that includes bits to be loaded into SFFs 106.
Each SFF 106 has two inputs A, B and an output Q, and selects one of the inputs A, B based on a scan shift signal applied to a scan input S. Each A input is connected to logic circuits 102. Each B input is connected to the output Q of a previous SFF 106 in the scan chain 104, except for the input B of the first SFF 106 in the scan chain 104, which is connected to a scan input node, such as a scan input terminal of integrated circuit 100, that can receive a scan input signal such as a test vector. The Q output of each SFF 106 in scan chain 104 is connected both to logic circuits 102 and to the next SFF 106 in scan chain 104, except for the output Q of the last SFF 106 in scan chain 104, which is connected both to logic circuits 102 and to a scan output node, such as a scan output terminal of integrated circuit 100, to provide a scan output signal.
When the scan shift signal is negated (for example, during normal operations), each SFF 106 in scan chain 104 gates signals to and from logic circuits 102 in response to a clock signal applied to a clock input of each SFF 106. However, when the scan shift signal is asserted (for example, during scan testing), each SFF 106 gates signals from the previous SFF 106 in the scan chain 104 to the next SFF 106 in the scan chain 104 in response to the clock signal, thereby causing the SFFs 106 to interconnect serially, forming scan chain 104.
During scan test, the scan shift signal is asserted, thereby forming the scan chain 104. Then the test vector (also referred to as “scan data”) is shifted into scan chain 104 as the scan input signal through the first SFF 106A in scan chain 104 in response to the clock signal. The scan shift signal is then negated, breaking scan chain 104 and restoring normal operational connections to SFF 106. The clock signal is then toggled one or more times to simulate normal operation of the integrated circuit 100. The scan shift signal is then asserted again, forming scan chain 104 again. Then the data in the SFFs 106 are shifted out of the scan chain as the scan output signal through the last SFF 106N in the scan chain in response to the clock signal. The scan output signal is then compared to a predetermined result vector to obtain a test result.
However, as the number of logic circuits in modern integrated circuits has grown, so has the number of storage elements required to test these logic circuits. The number of scan chains is limited by the number of terminals of the integrated circuit. Therefore, the length of each scan chain (that is, the number of storage elements in a scan chain) has increased. In general, the test time is defined by the length of the scan chains because most of the test cycles are consumed by shifting scan data into, and out of, the scan chains. Thus modern integrated circuits require increasingly greater test times.